AT87251G2D-3CSUM【PDF 21/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

Notes:

1. Logical instructions that affect a bit are in Table 27.

2. A shaded cell denotes an instruction in the C51 Architecture.

3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.

4. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).

6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 23.

Summary of Logical Instructions (2/2)

Note:

1. A shaded cell denotes an instruction in the C51 Architecture.

Shift Left LogicalSLL <dest><dest>0 ← 0

<dest>n+1 ← <dest>n, n = 0..msb-1

(CY)

← <dest>msb

Shift Right ArithmeticSRA <dest><dest>msb ← <dest>msb

<dest>n-1 ← <dest>n, n = msb..1

(CY)

← <dest>0

Shift Right LogicalSRL <dest><dest>msb ← 0

<dest>n-1 ← <dest>n, n = msb..1

(CY)

← <dest>0

SwapSWAP AA3:0 A7:4

Mnemonic

<dest>,

<src>

(1)

Comments

Binary Mode

Source Mode

Bytes

States

Bytes

States

SLL

Shift byte register left through the

MSB

WRj

Shift word register left through the

MSB

SRA

Shift byte register right

WRj

Shift word register right

SRL

Shift byte register left

WRj

Shift word register left

SWAP

Swap nibbles within ACC

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